Add VHDL to functionList.xml
Add VHDL to functionList.xml supporting ENTITY, BLOCK, PROCESS, COMPONENT, ARCHITECTURE. Close #8480, close #8509
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PowerEditor/Test/FunctionList/VHDL/unitTest
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35
PowerEditor/Test/FunctionList/VHDL/unitTest
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entity ent1 is
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end entity ent1;
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architecture rtl of ent1 is
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component compo1 is
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PORT ( Reset_s : out std_logic);
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end component compo1;
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component reset_controller is -- comment
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PORT -- comment
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( Reset_s : out std_logic);
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end component reset_controller; -- comment
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begin
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compo1_inst : compo1
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PORT MAP ( Reset_s =>open);
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rst_controller_inst : component reset_controller
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PORT MAP ( Reset_s => open); -- comment
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proc1: process (reset_reset_n, clk_clk)
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begin
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end process;
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block1: block is
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begin
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end block;
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comp_per_entity : entity work.doing_so port map ( Reset_s => open
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);
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end architecture rtl; -- of ent1
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{"leaves":["entity ent1 is","architecture rtl of ent1 is","\tcomponent compo1 is"," component reset_controller is ","proc1: process (reset_reset_n, clk_clk)"," block1: block is","comp_per_entity : entity work.doing_so port map ( Reset_s "],"root":"unitTest"}
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@ -15,6 +15,7 @@
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..\..\bin\notepad++.exe -export=functionList -lpowershell .\powershell\unitTest | Out-Null
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..\..\bin\notepad++.exe -export=functionList -lpython .\python\unitTest | Out-Null
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..\..\bin\notepad++.exe -export=functionList -lruby .\ruby\unitTest | Out-Null
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..\..\bin\notepad++.exe -export=functionList -lvhdl .\vhdl\unitTest | Out-Null
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..\..\bin\notepad++.exe -export=functionList -lxml .\xml\unitTest | Out-Null
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@ -85,6 +85,7 @@
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<association id= "nsis_syntax" langID="28" />
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<association id= "assembly_subroutine" langID="32" />
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<association id= "ruby_syntax" langID="36" />
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<association id= "vhdl_syntax" langID="38" />
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<association id= "autoit3_function" langID="40" />
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<association id= "innosetup_syntax" langID="46" />
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<!--
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@ -937,6 +938,34 @@
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</function>
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</parser>
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<!-- ======================================================== [ VHDL ] -->
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<!--
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| Derived from :
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| https://community.notepad-plus-plus.org/topic/11554/function-list-for-vhdl
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\-->
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<parser
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displayName="VHDL"
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id ="vhdl_syntax"
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>
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<function
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mainExpr="(?x) # free-spacing (see `RegEx - Pattern Modifiers`)
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^ # match at beginning of line
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\h* # optional leading whitespace
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(\w+\h*:)? # ID of process
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(?:\h(?!END)\w+\h)* # make sure this is not the end of a module
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\h*
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(?(1)(?:ENTITY|BLOCK|PROCESS)| # keywords if ':' was detected before
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(?:ENTITY|COMPONENT|ARCHITECTURE)) # keywords else
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[\h\(]+ # expect at least one blank or parentheses
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[A-Za-z0-9_\(\)., ]+ # ID or sensitivity list
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(?!\;)"
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>
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<functionName>
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<nameExpr expr=".*" />
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</functionName>
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</function>
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</parser>
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<!-- ===================================================== [ AutoIt3 ] -->
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<!--
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