From ffd6bb0889c715803ebc9c2bde1a6bd251ecdd11 Mon Sep 17 00:00:00 2001
From: Simon Buhrow <40995132+el-coder-sb@users.noreply.github.com>
Date: Thu, 2 Jul 2020 11:52:37 +0200
Subject: [PATCH] Add VHDL to functionList.xml

Add VHDL to functionList.xml supporting ENTITY, BLOCK, PROCESS, COMPONENT, ARCHITECTURE.

Close #8480, close #8509
---
 PowerEditor/Test/FunctionList/VHDL/unitTest   | 35 +++++++++++++++++++
 .../VHDL/unitTest.expected.result             |  1 +
 .../Test/FunctionList/unitTestLauncher.ps1    |  1 +
 PowerEditor/src/functionList.xml              | 29 +++++++++++++++
 4 files changed, 66 insertions(+)
 create mode 100644 PowerEditor/Test/FunctionList/VHDL/unitTest
 create mode 100644 PowerEditor/Test/FunctionList/VHDL/unitTest.expected.result

diff --git a/PowerEditor/Test/FunctionList/VHDL/unitTest b/PowerEditor/Test/FunctionList/VHDL/unitTest
new file mode 100644
index 00000000..db48481f
--- /dev/null
+++ b/PowerEditor/Test/FunctionList/VHDL/unitTest
@@ -0,0 +1,35 @@
+entity ent1 is
+end entity ent1;
+
+architecture rtl of ent1 is
+	component compo1 is
+    PORT ( Reset_s : out std_logic);
+	end component compo1;
+
+    component reset_controller is       -- comment
+    PORT                                -- comment
+    ( Reset_s : out std_logic);
+	end component reset_controller;     -- comment
+
+begin
+
+	compo1_inst : compo1
+    PORT MAP ( Reset_s =>open);
+
+	rst_controller_inst : component reset_controller
+    PORT MAP ( Reset_s => open);        -- comment
+
+
+
+proc1: process (reset_reset_n, clk_clk)
+    begin
+    end process;
+
+    block1: block is
+    begin
+    end block;
+
+comp_per_entity : entity work.doing_so port map ( Reset_s => open
+    );
+
+end architecture rtl; -- of ent1
diff --git a/PowerEditor/Test/FunctionList/VHDL/unitTest.expected.result b/PowerEditor/Test/FunctionList/VHDL/unitTest.expected.result
new file mode 100644
index 00000000..4281ad49
--- /dev/null
+++ b/PowerEditor/Test/FunctionList/VHDL/unitTest.expected.result
@@ -0,0 +1 @@
+{"leaves":["entity ent1 is","architecture rtl of ent1 is","\tcomponent compo1 is","    component reset_controller is       ","proc1: process (reset_reset_n, clk_clk)","    block1: block is","comp_per_entity : entity work.doing_so port map ( Reset_s "],"root":"unitTest"}
diff --git a/PowerEditor/Test/FunctionList/unitTestLauncher.ps1 b/PowerEditor/Test/FunctionList/unitTestLauncher.ps1
index 7298f009..2d8ff79b 100644
--- a/PowerEditor/Test/FunctionList/unitTestLauncher.ps1
+++ b/PowerEditor/Test/FunctionList/unitTestLauncher.ps1
@@ -15,6 +15,7 @@
 ..\..\bin\notepad++.exe -export=functionList -lpowershell .\powershell\unitTest | Out-Null
 ..\..\bin\notepad++.exe -export=functionList -lpython .\python\unitTest | Out-Null
 ..\..\bin\notepad++.exe -export=functionList -lruby .\ruby\unitTest | Out-Null
+..\..\bin\notepad++.exe -export=functionList -lvhdl .\vhdl\unitTest | Out-Null
 ..\..\bin\notepad++.exe -export=functionList -lxml .\xml\unitTest | Out-Null
 
 
diff --git a/PowerEditor/src/functionList.xml b/PowerEditor/src/functionList.xml
index b4aab2ec..ea4e1667 100644
--- a/PowerEditor/src/functionList.xml
+++ b/PowerEditor/src/functionList.xml
@@ -85,6 +85,7 @@
 			<association id=        "nsis_syntax"     langID="28"                          />
 			<association id=    "assembly_subroutine" langID="32"                          />
 			<association id=        "ruby_syntax"     langID="36"                          />
+			<association id=        "vhdl_syntax"     langID="38"                          />
 			<association id=     "autoit3_function"   langID="40"                          />
 			<association id=   "innosetup_syntax"     langID="46"                          />
 			<!--
@@ -937,6 +938,34 @@
 				</function>
 			</parser>
 
+			<!-- ======================================================== [ VHDL ] -->
+			<!--
+			|   Derived from :
+			|       https://community.notepad-plus-plus.org/topic/11554/function-list-for-vhdl
+			\-->
+			<parser
+				displayName="VHDL"
+				id         ="vhdl_syntax"
+			>
+				<function
+					mainExpr="(?x)                                          # free-spacing (see `RegEx - Pattern Modifiers`)
+						  ^                                             # match at beginning of line
+						  \h*                                           # optional leading whitespace
+						  (\w+\h*:)?                                    # ID of process
+						  (?:\h(?!END)\w+\h)*                           # make sure this is not the end of a module
+						  \h*
+						  (?(1)(?:ENTITY|BLOCK|PROCESS)|                # keywords if ':' was detected before
+						  (?:ENTITY|COMPONENT|ARCHITECTURE))            # keywords else
+						  [\h\(]+                                       # expect at least one blank or parentheses
+						  [A-Za-z0-9_\(\)., ]+                          # ID or sensitivity list
+						  (?!\;)"
+				>
+					<functionName>
+					    <nameExpr expr=".*" />
+					</functionName>
+				</function>
+			</parser>
+
 			<!-- ===================================================== [ AutoIt3 ] -->
 
 			<!--